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參數(shù)資料
| 型號(hào)： | W9451GBDA-6 |
| 英文描述： | SDRAM|DDR|64MX64|CMOS|DIMM|184PIN|PLASTIC |
| 中文描述： | 內(nèi)存|復(fù)員| 64MX64 |的CMOS |內(nèi)存| 184PIN |塑料 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 284K |
| 代理商： | W9451GBDA-6 |
W9451GBDA-6
- 6 -
9. CAPACITANCE
(V
DD
= V
DD
Q = 2.5V
±
0.2V, f = 1 MHz, T
A
= 25
°
C, V
OUT (DC)
= V
DD
Q/2, V
OUT
(Peak to Peak) = 0.2V)
PARAMETER
SYMBOL
C
add-IN
MIN.
MAX.
24
UNIT
pF
Address Input Capacitance (A0
A12, BA0, BA1)
Command Input Capacitance (
RAS
,
CAS
,
WE
)
C
CMD-IN
24
pF
CS
signals Input Capacitance (
CS0
,
CS1
)
C
CS-IN
12
pF
CKE signal Input Capacitance (CKE0, CKE1)
C
CKE-IN
12
pF
CLK signals Input Capacitance (CLKn,
CLKn
)
C
CLK-IN
12
pF
DM/DQS/DQ Input capacitance (DM0
DM7, DQS0
7, DQ0
63)
C
I/O
5
pF
10. DC CHARACTERISTICS
PARAMETER
SYM.
MAX.
-6
UNIT
NOTES
OPERATING CURRENT: One Bank Active-Precharge; t
RC
= t
RC
min; t
CK
= t
CK
min;
DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs
changing once per clock cycle
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; t
RC
= t
RC
min;
CL=2.5; t
CK
= t
CK
min; I
OUT
=0mA; Address and control inputs changing once per clock
cycle.
PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down
mode; CKE < V
IL
max; t
CK
= t
CK
min; Vin = V
REF
for DQ, DQS and DM
I
DD0
1240
7
I
DD1
1240
7, 9
I
DD2P
32
IDLE FLOATING STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle; CKE > V
IH
min; Address and other control inputs changing once per clock cycle; Vin = Vref for
DQ, DQS and DM
I
DD2F
720
7
IDLE STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle; CKE > V
IH
min; t
CK
= t
CK
min; Address and other control inputs changing once per clock cycle; Vin > V
IH
min or
Vin < V
IL
max for DQ, DQS and DM
I
DD2N
720
7
IDLE QUIET STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle; CKE > V
IH
min; t
CK
= t
CK
min; Address and other control inputs stable; Vin > V
REF
for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode;
CKE < V
IL
max; t
CK
= t
CK
min
I
DD2Q
640
mA
7
I
DD3P
320
ACTIVE STANDBY CURRENT:
CS
> V
IH
min; CKE > V
IH
min; One Bank Active-
Precharge; t
RC
= t
RAS
max; t
CK
= t
CK
min; DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle; CL = 2.5; t
CK
= t
CK
min; I
OUT
= 0 mA
OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle; CL=2.5; t
CK
= t
CK
min; DQ,
DM and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT: t
RC
= t
RFC
min
SELF REFRESH CURRENT: CKE < 0.2V
RANDOM READ CURRENT: 4 Banks Active Read with activate every 20 nS, Auto-
Precharge Read every 20ns; Burst = 4; t
RCD
= 3; I
OUT
= 0mA; DQ, DM and DQS inputs
changing twice per clock cycle; Address changing once per clock cycle
I
DD3N
920
7
I
DD4R
1710
7, 9
I
DD4W
1710
7
I
DD5
I
DD6
1880
48
7
I
DD7
2520
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