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參數(shù)資料
| 型號(hào)： | W9425G6JB-5 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 13 MM, ROHS COMPLIANT, TFBGA-60 |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 852K |
| 代理商： | W9425G6JB-5 |
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W9425G6JB
Publication Release Date: Oct. 08, 2010
- 3 -
Revision A01
11.10 Auto-precharge Timing (Write Cycle) ................................................................................ 40
11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 41
11.12 Burst Read Stop (BL = 8) .................................................................................................. 41
11.13 Read Interrupted by Write & BST (BL = 8)........................................................................ 42
11.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 42
11.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 43
11.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43
11.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44
11.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46
11.23 Auto Refresh Cycle............................................................................................................ 47
11.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47
11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47
11.26 Self Refresh Entry and Exit Timing ................................................................................... 48
12. PACKAGE SPECIFICATION ....................................................................................................... 49
12.1 60 Ball TFBGA (8x13 mm
2) ............................................................................................... 49
13. REVISION HISTORY ................................................................................................................... 50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W9425G8DH-6 | 32M X 8 DDR DRAM, 0.7 ns, PDSO66 |
| W946432AD-6 | 2M X 32 DDR DRAM, 0.1 ns, PQFP100 |
| W947D6HBHX6E | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| W9602BB | PUSHBUTTON SWITCH, SPST, MOMENTARY, 10A, 28VDC, PANEL MOUNT-THREADED |
| W9605BB | PUSHBUTTON SWITCH, SPST, MOMENTARY, 10A, 28VDC, PANEL MOUNT-THREADED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9425G6JB-5 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ |
| W9425G6JB-5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9425G6JB-5I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ, IN |
| W9425G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 M × 4 BANKS × 16 BITS DDR SDRAM |
| W9425G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP-II 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY 制造商:Winbond 功能描述:16MX16,256MB DDR,250MHZ,2.5V , TSOP 66PIN GREEN |
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