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參數(shù)資料
| 型號： | W942508AH-8 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.8 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 283K |
| 代理商： | W942508AH-8 |
PRELIMINARY W942508AH
8M
×× 4 BANKS ×× 8 BIT DDR SDRAM
Publication Release Date: May 2001
- 1 -
Revision .0.0
GENERAL DESCRIPTION
W942508AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 8,388,608 words
× 4 banks × 8 bits. Using pipelined architecture and 0.175 m
process technology, W942508AH delivers a data bandwidth of up to 286M words per second (-7). To
fully comply with the personal computer industrial standard, W942508AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942508AH is ideal for main memory in
high performance applications.
FEATURES
2.5V
± 0.2V Power Supply
Up to 143 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2 and 2.5
Burst Length: 2, 4, and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power-Down
Write Data Mask
Write Latency = 1
8K Refresh cycles / 64 mS
Interface: SSTL-2
Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-7
-75
-8
tCK
Clock Cycle Time
CL=2
min.
7.5 nS
8 nS
10 nS
CL=2.5
min.
7 nS
7.5 nS
8 nS
tRAS
Active to Precharge Command Period
min.
45 nS
50 nS
tRC
Active to Ref/Active Command Period
min.
65 nS
70 nS
IDD1
Operation Current (Single bank)
max.
110mA
100mA
IDD4
Burst Operation Current
max.
165mA
155mA
150mA
IDD6
Self-Refresh Current
max.
3mA
相關PDF資料 |
PDF描述 |
|---|---|
| W942516AH-6 | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W942516CH-75 | 16M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| W9425G6DH-6F | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W9425G6DH-6I | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W9425G8EH-5 | 32M X 8 DDR DRAM, 0.7 ns, PDSO66 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W942508BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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