參數(shù)資料
型號: W925E240
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁數(shù): 24/66頁
文件大?。?/td> 930K
代理商: W925E240
W925E/C240
8-bit CID Microcontroller
Revision : A6
-24-
Release Date : 2002/7/2
COMPARATOR REGISTER
(initial=00H)
Bit:
7
-
6
-
5
-
4
-
3
2
1
-
0
RESC
REF
COMPEN
Mnemonic: COMPR
Result of the comparator. Set when positive analog input voltage is(VPOS or
1.0v internal regular output) higher than negative analog input voltage(VNEG)
RESC is a read only bit.
Address: BBh
RESC:
REF:
COMPEN:
REF=0 reference input from analog input voltage(VPOS/P4.4) pin.
REF=1 reference input from the internal regulator output.
COMPEN=0 Disable comparator
COMPEN=1 Enable comparator
IDLE RELEASED CONDITION REGISTER 1
(initial=00H)
Bit:
7
-
6
5
-
4
-
3
2
1
0
IRCS1
IRCT1
IRCX1
IRCT0
IRCX0
Mnemonic: IRC1
Address: BCh
One of the bit of IRC1 and IRC2 will be set by hardware to record the idle released condition
when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by
software.
IRCS1: Idle mode released by Serial port interrupt flag.
IRCT1: Idle mode released by Timer 1 interrupt flag.
IRCX1: Idle mode released by external interrupt 1 flag.
IRCT0: Idle mode released by Timer 0 interrupt flag.
IRCX0: Idle mode released by external interrupt 0 flag.
IDLE RELEASED CONDITION REGISTER 2
(initial=00H)
Bit:
7
-
6
-
5
4
3
2
1
0
IRCWDI IRCCOMP IRCDIV IRCCID IRCX3
IRCX2
One of the bit of IRC1 and IRC2 will be set by hardware to record the idle released condition
when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by
software.
IRCWDI: Idle mode released by Watchdog timer interrupt flag.
IRCCOMP: Idle mode released by comparator interrupt flag.
IRCDIV: Idle mode released by Divider interrupt flag.
IRCCID: Idle mode released by CID interrupt flag.
IRCX3: Idle mode released by External Interrupt 3 flag.
IRCX2: Idle mode released by External Interrupt 2 flag.
Mnemonic: IRC2
Address: BDh
CAS TONE PRESENT TIME REGISTER
(initial=0FH)
Bit:
Mnemonic: CASPT
7
6
5
4
3
2
1
0
CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0
The clock period of guard-time timer is 0.8582mS. The default alert tone present time is 12.87mS.
CASPT7-0: The pre-set data register for counting CAS tone present time. When CAS tone is
detected (ALGR low to high), the guard timer starts to up-count from 00H. As the
Address: BEh
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