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參數(shù)資料
| 型號： | W89C92P |
| 英文描述： | 10M CMOS Coaxial Transceiver |
| 中文描述： | 1000萬的CMOS收發(fā)同軸 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 169K |
| 代理商： | W89C92P |
W89C92
- 10 -
PCB Layout Guidelines
(1) V
DD
and V
SS
should be connected to ground and a -9V DC copper plane, respectively, to dissipate
the power heat. The overlapped power and ground copper plane form a coupling capacitor that can
decouple high frequency noise on the power line. The -9V DC and ground must be as close as
possible to V
DD
and V
SS
of the W89C92 to reduce line inductance. A good power plane layout will
improve the MTBF of the W89C92.
(2) The trace between the coaxial cable and RXI and the isolating diode should be made as short as
possible. All the metal traces and the copper plane should be as far as possible from the RXI trace. A
longer RXI trace will induce more shunt capacitance loading, while closer traces induce larger
capacitance. This extra capacitance may overload the coaxial cable beyond the 2 pF stated in the
IEEE 802.3 specification. The RXI trace should be made as thick as possible to reduce the line
inductance. The maximum length of the RXI trace, 4 cm, is recommended.
A Cheapernet MAU implementation with the TCC
9V (Isolated)
COAX
1.5K Each
DC to DC
Converter
+
_
5V
1
2
1
2
16
15
CSO+
CSO-
DI+
14
15
16
TXO
RXI
CLS
1N4148
11
12
13
W
8
9
C
9
2
T
C
C
V
V
ER-
ER+
1 k 1%
3
4
5
6
13
12
10
DI-
V
V
DO+
4
5
7
8
7
8
9
DO-
9
10
SQE
DD
SS
SS
SS
+
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