參數(shù)資料
型號(hào): W83L786G
廠商: Nuvoton Technology Corporation of America
文件頁(yè)數(shù): 29/57頁(yè)
文件大?。?/td> 812K
描述: IC H/W MONITOR 28-SSOP
標(biāo)準(zhǔn)包裝: 48
功能: 硬件監(jiān)控器
傳感器類型: 外部
感應(yīng)溫度: 外部傳感器
精確度: ±3°C(最小值)
拓?fù)洌?/td> ADC,風(fēng)扇控制,寄存器庫(kù)
輸出類型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
W83L786R/ W83L786G
Publication Release Date: March 06
  - 24 -
Revision0.8
INT# Status Register 1 - Index 41h , continued.
BIT
NAME
READ/WRITE
DESCRIPTION
3     VIN1_STS
Read Only
A one indicates a High or Low limit has been exceeded.
(VIN1) This bit is cleared when this register is read.
2     VCC_STS
Read Only
A one indicates a High or Low limit has been exceeded.
(VCC, +3.3V) This bit is cleared when this register is read.
1     VRAM_STS
Read Only
A one indicates a High or Low limit has been exceeded.
(VRAM) This bit is cleared when this register is read.
0     VCORE_STS
Read Only
A one indicates a High or Low limit has been exceeded.
(VCORE) This bit is cleared when this register is read.
8.3   INT# Status Register 2 - Index 42h
Power on default [7:0] = 0000, 0000 b
BIT
NAME
READ/WRITE
DESCRIPTION
7-2    Reserved
Read Only     Reserved.
1     FAN2_STS
Read Only
A   one   indicates   the   fan   count   limit   has   been
exceeded. This bit is cleared when this register is
read.
0     FAN1_STS
Read Only
A   one   indicates   the   fan   count   limit   has   been
exceeded. This bit is cleared when this register is
read.
8.4   INT# Mask Register 1 - Index 43h
Power on default <7:0> = 1101, 1110 b
BIT
NAME
READ/WRITE
DESCRIPTION
7     MAK_T2_INT
Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (Temperature 2)
6     MSK_T1_INT
Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (Temperature 1)
5     MSK_T0_INT
Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (Temperature 0)
4     MSK_VIN2_INT
Read/Write
A one disables the corresponding interrupt status
bit for SMI# interrupt. (VIN2)
3     MSK_VIN1_INT
Read/Write
A one disables the corresponding interrupt status
bit for SMI# interrupt. (VIN1)
2     MSK_VCC_INT
Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (VCC, +3.3V)
1     MSK_VRAM_INT     Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (VRAM)
0
MSK_VCORE_IN
T
Read/Write
A one disables the corresponding interrupt status bit for
SMI# interrupt. (VCORE)
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