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參數(shù)資料
| 型號(hào)： | W83194BR-P4X |
| 英文描述： | Step-less VIA P4X/P4M Main Clock Gen. |
| 中文描述： | 步少威盛P4X/P4M主時(shí)鐘創(chuàng) |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大小： | 731K |
| 代理商： | W83194BR-P4X |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
W83194BR-250
6.2.1 Register 0 : Frequency Select Register (default = 0)
Bit
7
@PowerUp
0
Pin
-
Description
0 = Normal
1 = Spread Spectrum enabled
SSEL2 (for frequency table selection by software via I
2
C)
SSEL1 (for frequency table selection by software via I
2
C)
SSEL0 (for frequency table selection by software via I
2
C)
0 = Selection by hardware
1 = Selection by software I
2
C - Bit 6:4, Bit2
SSEL4 (for frequency table selection by software via I
2
C)
SSEL3 (for frequency table selection by software via I
2
C)
0 = Running
1 = Tristate all outputs
6
5
4
3
0
0
0
0
-
-
-
-
2
1
0
0
0
0
-
-
-
6.2.2 Register 1 : CPU Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@PowerUp
1
1
1
1
1
1
1
1
Pin
44
45
47
48
35
38
39
42
Description
IOAPIC1 (Active / Inactive)
IOAPIC0 (Active / Inactive)
REF1 (Active / Inactive)
REF0 (Active / Inactive)
CPUCLK3
(Active / Inactive)
CPUCLK2
(Active / Inactive)
CPUCLK1
(Active / Inactive)
CPUCLK_F
(Active / Inactive)
6.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
7
@PowerUp
Pin
Description
1
1
1
1
1
1
1
1
20
18
17
16
14
13
11
10
PCICLK8 (Active / Inactive)
6
5
4
3
2
1
0
PCICLK7 (Active / Inactive)
PCICLK6 (Active / Inactive)
PCICLK5 (Active / Inactive)
PCICLK4 (Active / Inactive)
PCICLK3 (Active / Inactive)
PCICLK2 (Active / Inactive)
PCICLK1 (Active / Inactive)
Publication Release Date:April. 2002
- 7 - Revision 1.0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83194BR-PT | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEPLESS VIA PT MAIN CLOCK GENERATOR |
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| W83194BR-SD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:Winbond Clock Generator For INTEL P4 Springdale Series Chipset |
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