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參數(shù)資料
| 型號： | W83194BR-250 |
| 英文描述： | Step-less Frequency VIA Pro266/PL266 Clock Gen. |
| 中文描述： | 步無時鐘頻率威盛Pro266/PL266將軍 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 731K |
| 代理商： | W83194BR-250 |
W83194BR-250
4.3 I
2
C Control Interface
SYMBOL
PIN
I/O
FUNCTION
SDATA*
29
I/O
Serial data of I
2
C 2-wire control interface
Serial clock of I
2
C 2-wire control interface
SDCLK*
28
IN
4.4 Fixed Frequency Outputs
SYMBOL
PIN
I/O
FUNCTION
REF0
48
OUT
3.3V 14.318MHz reference clock.
REF1 / *FS4
47
I/O
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Latched input for FS4 at initial power up for H/W
selecting the output frequency of CPU,
AGP
and PCI
clocks (Default=1).
24_48MHz/FS2*
7
I/O
24MHz or 48MHz output clock.
Latched input for FS42at initial power up for H/W
selecting the output frequency of CPU,
AGP
and PCI
clocks (Default=1).
48MHz_1/ FS3*
6
I/O
48MHz / Latched input for FS3 at initial power up
for H/W selecting the output frequency of CPU,
AGP
and PCI clocks (Default=1).
4.5 Power Pins
SYMBOL
PIN
FUNCTION
VddLCPU,VddLAPIC
37,41,46
Power supply for CPU & IOAPIC, 2.5V or 3.3V.
Vdd48
5
Power supply for 48MHz output,3.3V.
VddA
24
Power supply for 3V_66 output, 3.3V.
VddP
15
Power supply for PCICLK, 3.3V.
VddR
Vdd
Vss
1
31
Power supply for REFX2, 3.3V.
Power for I2C CLK and DATA.
Circuit Ground.
2,8,12,19,25,30,36,
40,43
Publication Release Date:April. 2002
- 5 - Revision 1.0
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