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W812 IEEE 1394 Link Layer Controller
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Oki Semiconductor
Packet header check and decoding
Coordinate function with optional FIFO controller
Packet flow control for transmission and receiving
Byte-wide Serializer and Deserializer
During transmission, this block serializes an 8-bit byte into appropriate size of data according to the asso-
ciated transmission speed. During receiving, this block accumulates receiving data, deserialzies it, and
passes data one byte at a time to the Quadlet Serializer and Deserializer. This block also generates signal
pertaining to the Annex J states like start and end of a receive, states during transmit or receive. It controls
when to read and or write a byte from or to the Quadlet Serializer and Desirializer and when to compute
new CRC.
Quadlet Serializer and Deserializer
During transmission, this block serializes 32-bit data into four 1-byte data. During receiving, this block
deserialzies four 1-byte data at a time into a 32-bit quadlet.
Quadlet Buffer
This block is a FIFO-type storage area.
Link Core Controller State Machine
This machine performs link layer packet transmit and receive operations as described in Figure 6-19, of
IEEE Standard 1394-1995
.
CRC Generator and Checker
This block generates and checks the CRC. The 32-bit polynomial function is as follows:
G(x) = x(32) + x(26) + x(23) + x(22) + x(16) + x(12) + x(11) + x(10) + x(8) + x(7) + x(5) + x(4) + x(2) + x + 1
To run the W812 at 400 Mbps, this block uses a specialized scheme to achieve desired performance.