參數(shù)資料
型號(hào)： W78M64120SBI
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： PROM
英文描述： 8M X 64 FLASH 3.3V PROM, 120 ns, PBGA159
封裝： 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159
文件頁(yè)數(shù)： 23/50頁(yè)
文件大?。?/td> 1679K
代理商： W78M64120SBI
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
GENERAL DESCRIPTION
The W78M64VP-XSBX is a 512Mb, 3.3 volt-only Page
Mode memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls.
The device offers uniform 64 Kword (128Kb) Sectors:
PAGE MODE FEATURES
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
STANDARD FLASH MEMORY
FEATURES
The device requires a 3.3 volt power supply for both read
and write functions. Internally generated and regulated
voltages are provided for the program and erase operations
Page Mode Features
DEVICE OPERATIONS
This section describes the read, program, erase,
handshaking, and reset features of the Flash devices.
Operations are initiated by writing specic commands or
a sequence with specic address and data patterns into
the command registers ( see Table 38 and Table 39). The
command register itself does not occupy andy addressable
memory location; rather, it is composed of latches that store
the commands, along with the address and data information
needed to execute the command. The contents of the
register serves as input to the internal state machine and
the state machine outputs dictate the function of the device.
Writing incorrect address and data values or writing them in
an improper sequence may place the device in an unknown
state, in which case the system must pull the RESET# pin
low or power cycle the device to return the device to the
reading array data mode.
DEVICE OPERATION TABLE
The device must be setup appropriately for each operation.
Table 2 describes the required state of each control pin for
any particular operation.
READ
All memories require access time to output array data. In a
read operation, data is read from one memory location at
a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes
the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-
up or hardware reset. To read data from the memory array,
the system must rst assert a valid address on A22-A0,
while driving OE# and CE# to VIL. WE# must remain at
VIH. All addresses are latched on the falling edge of CE#.
Data will appear on DQ15-DQ0 after address access time
(tACC), which is equal to the delay from stable addresses
to valid output data.
The OE# signal must be driven to VIL. Data is output on
DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#, assuming the tACC
access time has been meet.
PAGE READ MODE
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. The page size of the device is
8 words. The appropriate page is selected by the higher
address bits A(22)-A3.
Address bits A2-A0 in word mode determine the specic
word within a page. The microprocessor supplies the
specic word location. The random or initial page access
is equal to tACC or tCE and subsequent page read accesses
(as long as the locations specied by the microprocessor
falls within that page) is equivalent to tACC. When CE# is
deasserted and reasserted for a subsequent access, the
access time is tACC or tCE. Fast page mode accesses are
obtained by keeping the “read-page addresses” constant
and changing the “intra-read page” addresses.
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