參數(shù)資料
型號: W78L33
文件頁數(shù): 3/14頁
文件大小: 131K
代理商: W78L33
W78L33
Publication Release Date: September 1998
- 3 -
Revision A1
PIN DESCRIPTION
P0.0
P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0
P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0
P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0
P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
T0 Timer 0 Input
T1 Timer 1 Input
P3.4
P3.5
P3.6
WR Data Write Strobe
P3.7
RD Data Read Strobe
P4.0
P4.3
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins.
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78L33 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
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