
W78L32
- 6 -
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78L32 is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
V
CC
V
SS
V
IN
T
A
T
ST
MIN.
-0.3
V
SS
-0.3
0
-55
MAX.
+7.0
V
CC
+0.3
70
+150
UNIT
V
V
°
C
°
C
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
(V
DD
V
SS
= 5V
±
10%, T
A
= 25
°
C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
PECIFICATION
MIN.
1.8
-
-
-
-
-
-
-50
UNIT
TEST CONDITIONS
MAX.
5.5
20
3
6
1.5
50
20
+10
Operating Voltage
Operating Current
V
DD
I
DD
V
mA
mA
mA
mA
μ
A
μ
A
μ
A
No load, V
DD
= 5.5V, 20 MHz
No load, V
DD
= 2.0V, 16 MHz
V
DD
= 5.5V, Fosc = 20 MHz
V
DD
= 2.0V, Fosc =16 MHz
V
DD
= 5.5V, Fosc = 20 MHz
V
DD
= 2.0V, Fosc = 16 MHz
V
DD
= 5.5V
V
IN
= 0V or V
DD
V
DD
= 5.5V
0 < V
IN
< V
DD
V
DD
= 5.5V
0V < V
IN
< V
DD
Idle Current
I
IDLE
Power Down Current
I
PWDN
Input Current
P1, P2, P3
Input Current
RST
Input Leakage Current
I
IN1
I
IN2
-10
+300
μ
A
P0,
EA
Logic 1 to 0 Transition
Current
P1, P2, P3
I
LK
-10
+10
μ
A
I
TL
[*4]
-500
-
μ
A
V
DD
= 5.5V
V
IN
= 2.0V