
W78E516B
Publication Release Date: February 2000
- 15 -
Revision A3
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
CP
), and actual parts will
usually experience less than a
±
20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER
Operating Speed
SYMBOL
Fop
MIN.
0
TYP.
-
MAX.
40
UNIT
MHz
NOTES
1
Clock Period
TCP
25
-
-
nS
2
Clock High
Tch
10
-
-
nS
3
Clock Low
Tcl
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
T
AAS
T
AAH
T
APL
MIN.
1 T
CP
-
1 T
CP
-
1 T
CP
-
-
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
NOTES
4
1, 4
4
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to
PSEN
Low
PSEN
Low to Data Valid
Data Hold after PSEN High
T
PDA
-
2 T
CP
nS
2
T
PDH
0
-
1 T
CP
nS
3
Data Float after PSEN High
ALE Pulse Width
T
PDZ
0
-
1 T
CP
nS
T
ALW
T
PSW
2 T
CP
-
3 T
CP
-
2 T
CP
3 T
CP
-
-
nS
nS
4
4
PSEN
Pulse Width
Notes:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to
PSEN
going high.
4. "
" (due to buffer driving delay and wire loading) is 20 nS.