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參數(shù)資料
| 型號： | W78E54C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 198K |
| 代理商： | W78E54C |
W78E54C/W78E054C
Publication Release Date: October 3, 2006
- 15 -
Revision A4
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a
±
20 nS variation. The numbers below represent the performance
expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
7.3.1 Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
F
OP
0
-
40
MHz
1
Clock Period
T
CP
25
-
-
nS
2
Clock High
T
CH
10
-
-
nS
3
Clock Low
T
CL
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
7.3.2 Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
T
AAS
1 T
CP
-
Δ
-
-
nS
4
Address Hold from ALE Low
T
AAH
1 T
CP
-
Δ
-
-
nS
1, 4
ALE Low to
PSEN
Low
T
APL
1 T
CP
-
Δ
-
-
nS
4
PSEN
Low to Data Valid
T
PDA
-
-
2 T
CP
nS
2
Data Hold after
PSEN
High
T
PDH
0
-
1 T
CP
nS
3
Data Float after
PSEN
High
T
PDZ
0
-
1 T
CP
nS
ALE Pulse Width
T
ALW
2 T
CP
-
Δ
2 T
CP
-
nS
4
PSEN
Pulse Width
T
PSW
3 T
CP
-
Δ
3 T
CP
-
nS
4
Notes:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to PSEN going high.
4. "
Δ
" (due to buffer driving delay and wire loading) is 20 nS.
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