參數(shù)資料
型號: W78E365F-24
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 23/35頁
文件大?。?/td> 186K
代理商: W78E365F-24
Preliminary W78E365
Publication Release Date: April 2001
- 23 -
Revision A1
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
T
AAS
1 T
CP
-
1 T
CP
-
1 T
CP
-
-
-
nS
4
Address Hold from ALE Low
T
AAH
-
-
nS
1, 4
ALE Low to
PSEN
Low
T
APL
-
-
nS
4
PSEN
Low to Data Valid
T
PDA
-
-
2 T
CP
nS
2
Data Hold after PSEN High
T
PDH
0
-
1 T
CP
nS
3
Data Float after PSEN High
T
PDZ
0
-
1 T
CP
nS
ALE Pulse Width
T
ALW
2 T
CP
-
3 T
CP
-
2 T
CP
-
nS
4
PSEN Pulse Width
T
PSW
3 T
CP
-
nS
4
Notes:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to PSEN going high.
4. "
" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
T
DAR
3 T
CP
-
-
3 T
CP+
nS
1, 2
RD Low to Data Valid
T
DDA
-
-
4 T
CP
nS
1
Data Hold from RD High
T
DDH
0
-
2 T
CP
nS
Data Float from RD High
T
DDZ
0
-
2 T
CP
nS
RD Pulse Width
T
DRD
6 T
CP
-
6 T
CP
-
nS
2
Notes:
1. Data memory access time is 8 T
CP
.
2. "
" (due to buffer driving delay and wire loading) is 20 nS.
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