參數(shù)資料
型號(hào)： W78C58-40
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, MROM, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 15/22頁(yè)
文件大?。?/td> 304K
代理商： W78C58-40
W78C58
Publication Release Date: December 1997
- 15 -
Revision A5
Notes:
1. P00-P07, P20-P27 remain stable through entire memory cycle.
2. Memory access time is 3 Tcp.
3. Data has been latched internally prior to /PSEN going high.
4.
is 20 ns (due to buffer driving delay and wire loading).
Data Read Cycle
External Data Memory Read Cycle
(see Figure 7)
PARAMETER
SYMBOL
T
DAR
MIN.
3 Tcp-
TYP.
3 Tcp
MAX.
3 Tcp+
UINT
nS
NOTES
1, 2
ALE Low to
RD
Low
RD
Low to Data Valid
T
DDA
-
-
4 Tcp
nS
1
Data Hold After
RD
High
T
DDH
0
-
2 Tcp
nS
Data Float After
RD
High
T
DDZ
0
-
2 Tcp
nS
RD
Pulse Width
T
DRD
6 Tcp-
6 Tcp
6 Tcp+
nS
2
Notes:
1. Data Memory access time is 5 Tcp.
2.
is 20 ns (due to buffer driving delay and wire loading.
Data Write Cycle
External Data Memory Write Cycle
(see Figure 8)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UINT
NOTE
ALE Low to
WR
Low
T
DAW
3 Tcp-
3 Tcp
3 Tcp+
nS
*
Data Valid to
WR
Low
T
DAD
1 Tcp-
-
-
nS
Data Hold After
WR
High
T
DWD
1 Tcp-
-
-
nS
WR
Pulse Width
T
DWR
6 Tcp-
6 Tcp
6 Tcp+
nS
*
*Note:
is 20 ns (due to buffer driving delay and wire loading)
Port Access Cycle
Port Access Cycle
(see Figure 9)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UINT
Port Input Setup to ALE Low
T
PDS
1Tcp
-
-
nS
Port Input Hold After ALE Low
T
PDH
0
-
-
nS
Port Output to ALE High
T
PDA
1Tcp-
-
-
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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