
W78C52C
- 6 -
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C52C is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
DC Power Supply
V
CC
V
SS
V
IN
-0.3
+7.0
V
Input Voltage
V
SS
-0.3
V
CC
+0.3
V
Operating Temperature
T
A
0
70
°
C
°
C
Storage Temperature
T
ST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
the device.
of
DC CHARACTERISTICS
V
CC
V
SS
= 5V
ó
10%, T
A
= 25
°
C, F
OSC
= 20 MHz unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
SPECIFICATION
UNIT
MIN.
MAX.
Operating Voltage
V
DD
4.5
5.5
V
Operating Current
I
DD
No load V
DD
= 5.5V
-
30
mA
Idle Current
I
IDLE
Idle mode V
DD
= 5.5V
-
6
mA
Power Down Current
I
PWDN
Power-down mode
V
DD
= 5.5V
-
50
μ
A
Input Current P1, P2, P3
I
IN1
V
DD
= 5.5V
V
IN
= 0V or V
DD
V
DD
= 5.5V
V
IN
= 2.0V
(*1)
-50
+10
μ
A
Logical 1-to-0 Transition
Current P1, P2, P3
(*1)
Input Current RST
(*2)
I
TL
-650
-
μ
A
I
IN2
V
DD
= 5.5V V
IN
= V
DD
V
DD
= 5.5V
0V<V
IN
<V
DD
-
+300
μ
A
μ
A
Input Leakage Current
P0,
EA
I
LK
-10
+10