參數(shù)資料
型號: W78C438
廠商: WINBOND ELECTRONICS CORP
英文描述: 8-BIT EMULATION MICROCONTROLLER
中文描述: 8位單片機(jī)仿真
文件頁數(shù): 9/28頁
文件大小: 272K
代理商: W78C438
W78958B
Publication Release Date: September 1997
- 9 -
Revision A3
P8.7
P8.0 Port 8, Bits 7
0, Input/Output
TYPE
Advanced
MODE
Normal
DESCRIPTION
Functions are the same as those of Port 1 in the W78C31, except
that they are mapped by the P8 register and not bit-addressable. The
P8 register is not a standard register in the W78C32. Its address is at
0A6H.
Frozen in the original state.
P8.1 (ROMS1, standard type ROM size Select 1) and P8.0 (ROMS0)
are the input pins that determine which of four different ROM sizes is
being used: 4K, 8K, 16K, or 32K bytes. For details, see Table D1
D4.
Frozen in the original state.
Emulation
Normal
Standard
Emulation
INT2 and INT3 External Interrupt 2 and 3, Input
TYPE
Advanced
MODE
Normal
DESCRIPTION
Functions are similar to those of external interrupt 0 and 1 in the
W78C31, except that the functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt
Control) register. For details, see Table D6. The XICON register is
bit-addressable but is not a standard register in the W78C32. Its
address is at 0C0H. The interrupt vector addresses and the priority
polling sequence within the same level are shown in Table D7.
Frozen in the original state.
Not supported.
Emulation
-
Standard
BIT
7
ADDR.
0C7H
NAME
PX3
FUNCTION
High/low priority level for
INT 3
is specified when this bit is
set/cleared by software.
Enable/disable interrupt from INT3 when this bit is set/cleared by
software.
If IT3 is "1," IE3 is set/cleared automatically by hardware when
interrupt is detected/serviced.
INT3 is falling-edge/low-level triggered when this bit is set/cleared by
software.
High/low priority level for
INT 2
is specified when this bit is
set/cleared by software.
Enable/disable interrupt from
INT 2
when this bit is set/cleared by
software.
If IT2 is "1," IE2 is set/cleared automatically by hardware when
interrupt is de0tected/serviced.
INT 2
is falling-edge/low-level triggered when this bit is set/cleared
by software.
6
0C6H
EX3
5
0C5H
IE3
4
0C4H
IT3
3
0C3H
PX2
2
0C2H
EX2
1
0C1H
IE2
0
0C0H
IT2
Table D6. Functions of XICON Register.
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