參數(shù)資料
型號: W78C052D
廠商: WINBOND ELECTRONICS CORP
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 8/21頁
文件大小: 280K
代理商: W78C052D
W78C52D/W78C052D
- 8 -
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (
INT2
/
INT3
).
Example: P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0
P4.3.
MOV A, P4 ; Read P4 status to Accumulator.
SETB P4.0 ; Set bit P4.0
CLR P4.1 ; Clear bit P4.1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the time-
out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is
as a system monitor. This is important in real-time control applications. In case of power glitches or
electro-magnetic interference, the processor may begin to execute errant code. If this is left
unchecked the entire system may crash. The watchdog time-out selection will result in different time-
out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general,
software should restart the Watchdog timer to put it into a known state. The control bits that support
the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW
CLRW
WIDL
PS2
PS1
PS0
Mnemonic: WDTC Address: 8FH
ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
0 0 0
0 1 0
0 0 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PRESCALER SELECT
2
4
8
16
32
64
128
256
The time-out period is obtained using the following formula :
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