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參數(shù)資料
| 型號： | W78C052D40DL |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | ROHS COMPLIANT, DIP-40 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 280K |
| 代理商： | W78C052D40DL |
W78C52D/W78C052D
Publication Release Date: December 4, 2006
- 13 -
Revision A5
8. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a
±
20 nS variation. The numbers below represent the performance expected
from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
Clock Period
Clock High
Clock Low
F
OP
T
CP
T
CH
T
CL
0
25
10
10
-
-
-
-
40
-
-
-
MHz
nS
nS
nS
1
2
3
3
Notes
:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
SYMBOL
T
AAS
T
AAH
T
APL
MIN.
1 T
CP
-
1 T
CP
-
1 T
CP
-
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
NOTES
4
1, 4
4
ALE Low to
PSEN
Low
PSEN
Low to Data Valid
T
PDA
-
-
2 T
CP
nS
2
Data Hold after
PSEN
High
T
PDH
0
-
1 T
CP
nS
3
Data Float after
PSEN
High
ALE Pulse Width
T
PDZ
0
-
1 T
CP
nS
T
ALW
T
PSW
2 T
CP
-
3 T
CP
-
2 T
CP
3 T
CP
-
-
nS
nS
4
4
PSEN
Pulse Width
Notes
:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to
PSEN
going high.
4. "
" (due to buffer driving delay and wire loading) is 20 nS.
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