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參數(shù)資料
| 型號： | W6811IWG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PDSO24 |
| 封裝： | 4.40 X 7.80 MM, ROHS COMPLIANT, PLASTIC, TSSOP1-24 |
| 文件頁數(shù)： | 4/37頁 |
| 文件大?。?/td> | 589K |
| 代理商： | W6811IWG |
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W6811
Publication Release Date: September, 2005
- 12 -
Revision A12
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not
used for data transmission and also in the time slot of the unused channels. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
master clock rates. The system clock is supplied through the master clock input MCLK and can be
derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and an
8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for
the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811
will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW.
When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame
Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become
low impedance.
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| W6811IWG TR | 功能描述:IC VOICEBAND CODEC 5V/3V 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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| W681307 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM |
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