參數(shù)資料
型號： W6811ISG
廠商： WINBOND ELECTRONICS CORP
元件分類： 編解碼器
英文描述： A/MU-LAW, PCM CODEC, PDSO24
封裝： 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-24
文件頁數(shù)： 37/37頁
文件大?。?/td> 589K
代理商： W6811ISG
W6811
Publication Release Date: September, 2005
- 9 -
Revision A12
AI+
Input Amplifier
Input
VDDA
Powered Down
AO
1.2 to VDDA-1.2
Powered Up
AI+, AI-
VSSA
Powered Down
AI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG.
The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent
aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low
pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed
according to the recommendations in the G.712 ITU-T specification. From the output of the high pass
filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with
either
μ-Law or A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin.
The compression format can be selected according to Table 7.2.
μ/A-Law Pin
Format
VSSA
A-Law
VDDA
μ-Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit
μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
data rate supplied by the external bit clock BCLKT.
7.2. RECEIVE PATH
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable
μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the
μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO-. The RO- output can be externally connected to the
PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By
using external resistors (see section 11 for examples), various gain settings of this output amplifier can
be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to
VDDA.
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