參數(shù)資料
型號(hào)： W671371Y
廠商： WINBOND ELECTRONICS CORP
元件分類： 模擬傳輸電路
英文描述： TELECOM-SLIC, QCC32
封裝： QFN-32
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 1344K
代理商： W671371Y
W671300 SERIES
differential ringing gain of the device is 80V/V. The circuit model for the ringing path is shown in the
following figure.
The voltage gain from the VRS input to the TIP output is 40V/V. The resistor ratio provides a gain of 8
and the current mirror provides a gain of 5. The voltage gain from the VRS input to the RING output is
-40V/V.
TIP
RING
VRS
R/8
R
+
-
+-
5:1
20
+-
+
-
600K
V
BH
2
FIGURE 12: LINEAR RINGING MODEL
The equations for the TIP and RING outputs during ringing are provided below.
VT
VBH
2
-----------
40 VRS
×
(
)
+
=
(EQ. 55)
VR
VBH
2
-----------
40 VRS
×
(
)
=
(EQ. 56)
When the input signal at VRS is zero, the Tip and Ring amplifier outputs are centered at half battery.
The device provides auto centering for easy implementation of sinusoidal ringing waveforms. Both AC
and DC control of the Tip and Ring outputs are available during ringing. This feature allows for DC
offsets as part of the ringing waveform.
7.2.4.2. Ringing Signal Input
The Ringing Signal Input, VRS, is a high impedance input. The high impedance allows the use of low
value capacitors for AC coupling of the ring signal. The VRS input is enabled only during the Ringing
mode, therefore a free running oscillator may be connected to VRS at all times.
When operating from a battery of -100V, each amplifier, Tip and Ring, will swing a maximum of 95VP-
P. Hence, the maximum signal swing at VRS to achieve full scale ringing is approximately 2.4VP-P. The
low signal levels are compatible with the output voltage range of the CODEC.
- 28 -
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