參數(shù)資料
型號： W6690
廠商： WINBOND ELECTRONICS CORP
英文描述： ISDN S/T Interface Controller(ISDN S/T接口控制器)
中文描述： 綜合業(yè)務數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務數(shù)字網(wǎng)S / T的接口控制器）
文件頁數(shù)： 1/76頁
文件大小： 471K
代理商： W6690
Preliminary W6690
ISDN S-CONTROLLER
Publication Release Date: March 1998
- 1 -
Revision A1
Table of Contents--
1. GENERAL DESCRIPTION..........................................................................................................................4
2. FEATURES..................................................................................................................................................4
3. PIN CONFIGURATIONS..............................................................................................................................5
4. PIN DESCRIPTION......................................................................................................................................7
5. SYSTEM DIAGRAM AND APPLICATIONS ..............................................................................................10
6. BLOCK DIAGRAM.....................................................................................................................................12
7. FUNCTIONAL DESCRIPTIONS................................................................................................................12
7.1 Main Block Functions............................................................................................................................12
7.2 Layer 1 Functions Descriptions.............................................................................................................13
7.2.1 S/T Interface Transmitter/Receiver ..................................................................................................13
7.2.2 Receiver Clock Recovery And Timing Generation............................................................................17
7.2.3 Layer 1 Activation/Deactivation .......................................................................................................17
7.2.4 D Channel Access Control...............................................................................................................22
7.2.5 Frame Alignment.............................................................................................................................22
7.2.6 Multiframe Synchronization.............................................................................................................25
7.2.7 Test Functions ................................................................................................................................27
7.3 Serial Interface Bus ..............................................................................................................................28
7.4 B Channel Switching.............................................................................................................................28
7.5 PCM Port..............................................................................................................................................29
7.6 D Channel HDLC Controller .................................................................................................................29
7.6.1 D Channel Message Transfer Modes...............................................................................................30
7.6.2 Reception of Frames in D Channel..................................................................................................31
7.6.3 Transmission of Frames in D Channel.............................................................................................31
7.7 B Channel HDLC Controller..................................................................................................................32
7.7.1 Reception of Frames in B Channel ..................................................................................................32
7.7.3 Transmission of Frames in B Channel.............................................................................................33
7.8 ISA Plug and Play Controller/Micro-processor Interface.......................................................................34
7.8.1 Modes of Operations.......................................................................................................................34
7.8.2 Cascade Structure of Interrupt Sources...........................................................................................35
8. REGISTER DESCRIPTIONS.....................................................................................................................38
8.1 Chip Control and D_ch HDLC Controller..............................................................................................38
8.1.1 D_ch receive FIFO D_RFIFO Read Address 00H............................................................................40
8.1.2 D_ch transmit FIFO D_XFIFO Write Address 01H..........................................................................40
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