W551Cxxx Data Sheet
Winbond Electronics Corp.
6
Release Date:
January 2, 2001
Function Description
3.1 W551Cxxx Functional Description
The maximum number of the ADDR clock is 24 bits. The address data is shifted into the 24 bits address counter
by the ADDR clock. The MSB x bits of the address counter are the page codes, and the rest (24 - x) bits are the bit
of address. Note that the MSB is shifted first. The MSB 5 bits of the address counter are always gating (exclusive
OR) with the content of the page-code cells to determine whether these two articles are match or not. Only when the
page codes are matched with the content of the page-code cells, this device can be enabled. The counting source of
the address counter is the CLK clock, the falling edge signal of the CLK clock up-count the counter.
In normal-read mode the ADDR and CLK clock cannot be active simultaneously. The first rising edge signal of
the ADDR clock after CLK clocking will reset the address shift registers. The following table describes the needed
bits of
″
page code
″
:
Part #
W551C002
W551C005
W551C010
W551C020
W551C040
W551C060
W551C080
Density
256K bits
512K bits
1M bits
2M bits
4M bits
6M bits
8M bits
Bits of
page code
6
5
4
3
2
2
1