參數(shù)資料
型號: W49L401TS70B
元件分類: EEPROM
英文描述: EEPROM
中文描述: EEPROM的
文件頁數(shù): 4/24頁
文件大小: 307K
代理商: W49L401TS70B
W49L401(T)
- 4 -
Block/Page Erase Operation
The W49L401(T) provides both uniform small page (2K-word) and non-symmetrical block
(4K/8K/16K/32K-word) erase capabilities for versatile Flash applications.
Each block or page can be erased individually by initiating a six-word command sequence. The block
address (BA) or page address (PA) is latched on the falling #WE edge of the sixth cycle while the
XX30/XX50(hex) data input command is latched at the rising edge of #WE. After the command loading
cycle, the device enters the internal block/page erase mode, which is automatically timed and will be
completed in a fast 50 mS (typical). The host system is not required to provide any control or timing
during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data-polling, Toggle-Bit and/or RY/#BY pin can be used to detect end of erase
cycle.
The bootblock (8K-words) consists of 4 corresponding uniform pages of 2K-words each. When the
boot block lockout feature is activated, any page/block erase command with the associated PA/BA
within the bootblock address range (0000-01FFF for W49L401, and 3E000-3FFFF for W49L401T) will
be ignored and the device will return to read mode without any data changes.
Program Operation
The W49L401(T) is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in individual page/block or whole
chip from "0" to "1") is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50
μ
S max. -
T
BP
) once completed and return to normal read mode. Data_polling, Toggle_Bit and/or RY/#BY pin
can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49L401(T) is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 10 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation and read are inhibited when V
DD
is
less than 1.8V typical.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out
10 mS before any write (erase/program) operation.
Data Polling (DQ
7
)- Write Status Detection
The W49L401(T) includes a data polling feature to indicate the end of a program or erase cycle.
When the W49L401(T) is in the internal program or erase cycle, any attempt to read DQ
7
of the last
word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
7
will show the true data. Note that, DQ
7
will show logical "0" during the erase cycle.
And it will become logical "1" or true data when the erase cycle is completed.
Toggle Bit (DQ
6
)- Write Status Detection
In addition to data polling, the W49L401(T) provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will
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