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參數(shù)資料
| 型號： | W48S87-04 |
| 廠商： | IC WORKS INC |
| 元件分類： | XO, clock |
| 英文描述： | Spread Spectrum 3 DIMM Desktop Clock(寬頻譜3 DIMM桌上型PC機(jī)時(shí)鐘) |
| 中文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大小： | 200K |
| 代理商： | W48S87-04 |
PRELIMINARY
Spread Spectrum 3 DIMM Desktop Clock
W48S87-04
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 19, 1999, rev. **
Features
Outputs
—4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz)
—7 PCI (3.3V)
—1 48-MHz for USB (3.3V)
—1 24-MHz for Super I/O (3.3V)
—2 REF (3.3V)
—1 IOAPIC (2.5V or 3.3V)
—12 SDRAM
Serial data interface provides additional frequency
selection, individual clock output disable, and other
functions
Smooth transition supports dynamic frequency
assignment
Frequency selection not affected during power
down/up cycle
Supports a variety of power-saving options
3.3V operation
Available in 48-pin SSOP (300 mils)
Key Specifications
±0.5% Spread Spectrum Modulation: ......................... ±0.5%
Jitter (Cycle-to-Cycle):.................................................250 ps
Duty Cycle:................................................................45-55%
CPU-PCI Skew:........................................................1 to 4 ns
PCI-PCI or CPU-CPU Skew:.......................................250 ps
Table 1. Pin Selectable Frequency
[1]
Input Address
CPU, SDRAM
Clocks (MHz)
FS2
FS1
FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Notes:
1.
2.
Additional frequency selections provided by serial data interface; refer to
Table 5
on page 10.
Signal names in parenthesis denotes function is selectable through mode pin register strapping.
PCI Clocks
(MHz)
25.0
32.0
41.65
34.25
27.5
37.5
30.0
33.4
50.0
75.0
83.3
68.5
55.0
75.0
60.0
66.8
Block Diagram
Pin Configuration
[2]
VDD1
IOAPIC
VDD3
SDRAM0:11
PCI_F/FS1
PCI0/FS2
XTAL OSC
PLL Ref
Freq
PLL1
X2
X1
REF1(CPU_STOP#)
Stop
Clock
Cntrl
PCI1:4
PWR_DWN#
Power Down
Control
PCI5(PWR_DWN#)
48MHZ/FS0
24MHZ/MODE
PLL2
Serial Port
SCLOCK
SDATA
Device
Control
CPU_STOP#
CPU3.3#_2.5
CPU Clock
Mode Control
÷4
÷2
I/O
I/O
VDD1
MODE
4
I/O
I/O
VDD2
12
CPU0:3
4
VDDL2
÷2
VDDL1
MODE
I/O
REF0/CPU3.3#_2.5
Freq
Select
FS0
FS1
FS2
VDD1
REF0/CPU3.3#_2.5
GND
X1
X2
VDD2
PCI_F/FS1
PCI0/FS2
GND
PCI1
PCI2
PCI3
PCI4
VDD2
PCI5(PWR_DWN#)
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLOCK
W
VDDL1
IOAPIC
REF1(CPU_STOP#)
GND
CPU0
CPU1
VDDL2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
GND
48MHZ/FS0
24MHZ/MODE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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