參數(shù)資料
型號: W42C32
廠商: Cypress Semiconductor Corp.
英文描述: Spread Spectrum Frequency Timing Generator
中文描述: 擴頻頻率定時發(fā)生器
文件頁數(shù): 1/8頁
文件大小: 131K
代理商: W42C32
Spread Spectrum Frequency Timing Generator
W42C32-05
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
September 28, 1999, rev. **
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Generates a spread spectrum timing signal
Reduces measured EMI by as much as 12 dB
Integrated loop filter components
Requires a single low-cost fundamental crystal (or
other frequency reference) for proper operation
Special spread spectrum control functions
Low-power CMOS design
Available in 16-pin SOIC package, (300 mil)
Overview
The W42C32 modulates the output of a single PLL in order to
‘spread’ the bandwidth of a synthesized clock and, more im-
portantly, decrease the peak amplitudes of its fundamental
harmonics. Since peak amplitudes are reduced, the radiated
electromagnetic emissions of the W42C32-05 are significantly
lower than the typical narrow band signal produced by oscilla-
tors and most frequency generators. Lowering a signal’s am-
plitude by increasing its bandwidth is a method of reducing
EMI called ‘spread spectrum frequency timing generation’.
This patented technique not only reduces the emissions of the
primary clock, but also impacts every signal synchronized to it.
Key Specifications
Cycle-to-Cycle Jitter ....................................................250 ps
45/55 Duty Cycle.................................... approximately 1.4V
Selectable Frequency spread
2 ns rise/fall time 0.4V to 2.0V, 3.3V supply
2 ns rise/fall time 0.8V to 2.4V, 5.0V supply
Table 1. Frequency Spread Selection
W42C32-05
REFOUT
(MHz)
22.1148
FS2
0
FS1
0
FS0
0
CLKOUT
(MHz)
44.2296 ±
2.5%
44.2296
±1.5%
29.4912 ±
2.5%
18.432 ± 2.5%
66.66 – 2%
Reserved
100 – 2%
Reserved
VDD
(V)
5.0
0
0
1
22.1148
5.0
0
1
0
14.7456
5.0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
18.432
14.318
5.0
3.3
3.3
3.3
3.3
14.318
Pin Configuration
W
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PD#
X1
X2
GND
AGND
FS0
TEST
CLKOUT
REFOUT
FS2
FS1
SSON#
RESET
VDD
AVDD
REFEN#
SOIC
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