參數(shù)資料
型號(hào): W3HG2128M72ACER534AD6MG
廠(chǎng)商: WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi): DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 305K
代理商: W3HG2128M72ACER534AD6MG
W3HG2128M72ACER-xAD6
PRELIMINARY
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
May 2007
Rev. 9
RECOMMENDED DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Parameter
Symbol
Rating
Units
Notes
Min.
Type
Max.
Supply Voltage
VCC
1.7
1.8
1.9
V
4
Supply Voltage for DLL
VCCL
1.7
1.8
1.9
V
4
Supply Voltage for Output
VCCQ
1.7
1.8
1.9
V
4
Input Reference Voltage
VREF
0.49*VCCQ
0.50*VCCQ
0.51*VCCQ
V
1, 2
Termination Voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
There is no specic device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VCCQ of the transmitting
device and VREF is expected to track variations in VCCQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VCC, VCCQ and VCCL are tied together on this module.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
Parameter
Rating
Units
Notes
VCC
Voltage on VCC pin relative to VSS
- 1.0 V - 2.3 V
V
5
VCCQ
Voltage on VCCQ pin relative to VSS
- 0.5 V - 2.3 V
V
5
VCCL
Voltage on VCCL pin relative to VSS
- 0.5 V - 2.3 V
V
5
VIN, VOUT
Voltage on any pin relative to VSS
- 0.5 V - 2.3 V
V
5
TSTG
Storage Temperature
-55 to +100
C
5, 6
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
CAPACITANCE
TA = 25°C, f = VREF = Gnd, f = 100MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
Max
Units
Input Capacitance: CK, CK#
CCK
5.6
pF
Input Capacitance: CKE, CS#
CI1
12.4
pF
Input Capacitance: Addr. RAS#, CAS#, WE#, ODT
CI2
12.4
pF
Input/Output Capacitance: DQ, DQS, DM, DQS#, CB
CIO
15.6
pF
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