參數(shù)資料
型號(hào)： W3HG2128M64EEU665XD4ISG
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 256M X 64 DDR DRAM MODULE, 0.45 ns, ZMA200
封裝： ROHS COMPLIANT, SODIMM-200
文件頁(yè)數(shù)： 10/13頁(yè)
文件大?。?/td> 188K
代理商： W3HG2128M64EEU665XD4ISG
W3HG2128M64EEU-D4
January 2008
Rev. 7
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATION
Symbol
Proposed Conditions
805
806
665
534
403
Units
ICC0*
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Normal
840
800
760
720
mA
Low Power
784
744
704
664
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS =
tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Normal
920
880
840
800
mA
Low Power
864
824
784
744
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
Normal
240
mA
Low Power
128
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
640
560
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
800
720
640
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit
MRS(12) = 0
640
560
mA
Slow PDN Exit
MRS(12) = 1
288
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1,040
960
880
mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK =
tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Normal
1,280
1,160
1,080
960
mA
Low Power
1,224
1,104
1,024
904
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL =
0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as ICC4W
Normal
1,360
1,240
1,160
1,040
mA
Low Power
1,304
1,184
1,104
984
ICC5*
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,480
2,400
2,320
mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal
240
mA
Low Power
96
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-
1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING.
Normal
2,240
2,200
2,040
1,920
mA
Low Power
2,184
2,144
1,984
1,864
ICC specication is based on
SAMSUNG 1G (D-die revision) components. Other DRAM manufactures specication may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reects all module ranks in this operating condition.
相關(guān)PDF資料
PDF描述
W3HG2128M64EEU806XD4SG 256M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
W3HG2128M64EEU403XD4MG SYNCHRONOUS DRAM MODULE, DMA200
W3HG2128M64EEU534XD4MG SYNCHRONOUS DRAM MODULE, DMA200
W3HG2128M64EEU806D4ISG 256M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
W3HG2128M72ACER534AD6MG 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3HG2128M72ACER403AD6XG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
W3HG2128M72ACER534AD6XG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
W3HG2128M72ACER665AD6XG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
W3HG2128M72ACER806AD6XG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
W3HG2128M72ACER-AD6 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*