參數(shù)資料
型號(hào): W3HG128M72AER665AD6IGG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝: ROHS COMPLIANT, RDIMM-240
文件頁(yè)數(shù): 12/12頁(yè)
文件大小: 190K
代理商: W3HG128M72AER665AD6IGG
W3HG128M72AER-AD6
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
ODT
AC CHARACTERISTICS
SYMBOL
806
665
534
403
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ODT turn-on delay
tAOND
TBD
222222
tCK
ODT turn-on
tAON
TBD
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC
(MIN) +
2,000
tAC
(MIN) +
2,000
2 x tCK
+ tAC
(MAX)
+ 1,000
tAC
(MIN) +
2,000
2 x tCK
+ tAC
(MAX)
+ 1,000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC
(MIN) +
2,000
2.5
x tCK
+ tAC
(MAX)
+ 1,000
tAC
(MIN) +
2,000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN) +
2,000
2.5
x tCK
+ tAC
(MAX)
+ 1,000
ps
ODT to power-down entry latency
tANPD
TBD
333
tCK
ODT power-down exit latency
tAXPD
TBD
888
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
TBD
222
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
TBD
7 - AL
6 - AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
TBD
222
tCK
CKE minimum high/low time
tCKE
TBD
333
tCK
Note: AC specication is based on
QIMONDA components. Other DRAM manufactures specication may be different
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
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