參數(shù)資料
型號(hào): W3HG128M72AER403AD6GG
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: ROHS COMPLIANT, RDIMM-240
文件頁(yè)數(shù): 11/12頁(yè)
文件大?。?/td> 190K
代理商: W3HG128M72AER403AD6GG
W3HG128M72AER-AD6
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
SYMBOL
806
665
534
403
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
Address and control input pulse width for
each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tIS
TBD
200
250
350
ps
Address and control input hold time
tIH
TBD
275
375
475
ps
CAS# to CAS# command delay
tCCD
TBD
222
tCK
ACTIVE to ACTIVE (same bank) command
tRC
TBD
60
55
ns
ACTIVE bank a to ACTIVE bank b
command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
ACTIVE to PRECHARGE command
tRAS
TBD
45
70,000
45
70,000
40
70,000
ns
Internal READ to precharge command
delay
tRTP
TBD
7.5
ns
6 Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge
time
tDAL
TBD
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
ns
LOAD MODE command cycle time
tMRD
TBD
222
tCK
OCD Drive mode delay
tOIT
TBD
0
12012
ns
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
ns
Refresh
REFRESH to REFRESH command interval
tRFC
TBD
105
70,000
105
70,000
ns
Average periodic refresh interval
tREF
TBD
7.8
μs
Self
Refresh
Exit self refresh to non-READ command
tXSNR
TBD
tRFC + 10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tISXR
TBD
250
350
ps
Continued on next page
Note: AC specication is based on
QIMONDA components. Other DRAM manufactures specication may be different
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