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參數(shù)資料
| 型號： | W3HG128M72AEF806F1SBG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG128M72AEF806F1SBG |
14
W3HG128M72AEF-Fx
September 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
14.
This number represents the lane-to-lane skew between TX and
RX pins and does not include the transmitter output skew from the
component driving the signal to the receiver. This is one component
of the end-to-end channel skew in the AMB specication.
15.
Measured from the reference clock edge to the center of the input
eye. This specication must be met across specied voltage and
temperature ranges for a single component. Drift rate of change is
signicantly below the tracking capability of the receiver.
16.
This bandwidth number assumes the specied minimum data
transition density. Maximum jitter at 0.2 MHz is 0.05 UI.
17.
The specied time includes the time required to forward the El entry
condition.
18.
BER per differential lane.
7.
This number does not include the effects of SSC or reference clock
jitter.
8.
This number includes setup and hold of the RX sampling op.
9.
Dened as the dual-dirac deterministic timing error.
10.
Allows for 15mV DC offset between transmit and receive devices.
11.
The received differential signal must satisfy both this ratio as well as
the absolute maximum AC peak-to-peak common mode specication.
For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-
to-peak common mode is the lesser of (200mV x 0.45=90mV) and
VRX-CM-AC-p-p.
12.
One of the components that contribute to the deterioration of the
return loss is the ESD structure which needs to be carefully designed.
13.
The termination small signal resistance; tolerance across voltages
from 100mV to 400mV shell not exceed +/- 5W with regard to the
average of the values measured at 100mV and at 400mV for that pin.
VRX-DIFFp-p = 2 x|VRX-D+ -VRX-D-|
(EQ 5)
VRX-CM = DC(avg) of (|VRX-D+ +VRX-D-|/(2)
(EQ 6)
VRX-CD-AC = ((Max|VRX-D+ +VRX-D-|)/(2) - ((Min |VRX-D++VRX-D-|)/2)
(EQ 7)
RRX-MATCH-DC = 2x ((|RRX-D+ -RRX-D-|)/(|RR-D++RRX-D-|))
(EQ 8)
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相關(guān)代理商/技術(shù)參數(shù) |
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| W3HG2128M72ACER403AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER534AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER665AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER806AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER-AD6 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
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