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參數(shù)資料
| 型號(hào)： | W3HG128M64EEU403D4IMG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.6 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | W3HG128M64EEU403D4IMG |
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W3HG128M64EEU-D4
November 2006
Rev. 2
ADVANCED*
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
t
CKAVG(MIN) is the smallest clock rate allowed, except a deviation due to allowed
clock jitter. Input clock jitter is allowed provided it does not exceed values specied.
Also, the jitter must be of a random Gaussian distribution in nature.
37. The inputs to the DRAM must be aligned to the associated clock; that is, the actual
clock that latches it in. However, the input timing (in ns) references to the tCKAVG
when determining the required number of clocks. The following input parameters are
determined by taking the specied percentage times the tCKAVG rather thank tCK:
t
IPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDH, tWPST, and tWPRE.
38. Spread spectrum is not included in the jitter specication values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz
with additional one percent of tCKAVG as a long-term jitter component; however,
the spread spectrum may not use a clock rate below tCKAVG(MIN) or above
t
CKAVG(MAX).
39. The period jitter (tJITPER) is the maximum deviation in the clock period from the
average or nominal clock allowed in either the positive or negative direction. JEDEC
species tighter jitter numbers during DLL locking time. During DLL lock time, the
jitter values should be 20 percent less than noted in the table (DLL locked).
40. The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low
pulse of clock; however, the two cumulatively can not exceed tJITPER.
41. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from
one cycle to the following cycle. JEDEC species tighter jitter numbers during DLL
locking time. During DLL lock time, the jitter values should be 20 percent less than
noted in the table (DLL locked).
42. The cumulative jitter error (tERRnPER) where n is 2, 3, 4, 5, 6–10, or 11–50, is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
43. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting tERR5PER(MAX): tAC(MIN), tDQSCK(MIN),
t
HZ(MIN), tLZDQ(MIN), tAON(MIN); while these following parameters are required
to be derated by subtracting tERR5PER(MIN): tAC(MAX), tDQSCK(MAX), tHZ(MAX),
t
LZDQ(MAX), tAON(MAX). The parameter tRPRE(MIN) is derated by subtracting
t
JITPER(MAX), while tPRPE(MAX), is derated by subtracting tJITPER(MAX) . The
parameter tRPST(MAX), is dated by subtracting tJITDTY(MIN).
44. Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY
when input clock jitter is present; this will result in each parameter becoming
larger. The parameter tAOF(MIN) is required to be derated by subtracting both
t
ERR5PER(MAX) and tJITPER(MAX). The parameter tAOF(MAX) is required to be
derated by subtracting both tERR5PER(MIN) and tJITDTY(MIN).
45. MIN(tCL, tCH) refers to the smaller of the actual clock LOW time and the actual
clock HIGH time driven to the device. The clock's half period must also be of a
Gaussian distribution; tCHAVG and tCLAVG must be met with or with our clock jitter
and with or without duty cycle jitter. tCHAVG and tCLAVG are the average of any 200
consecutive CK falling edges.
46. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#
inputs; thus, tHP(MIN) ≥ the lesser of tCLABS(MIN) and tCHABS(MIN).
47. tQH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS(MAX) or
t
CHABS(MAX) times tCKABS(MIN) - tQHS. Minimizing the amount of tCHAVG offset and
value of tJITDTY will provide a larger tQH, which in turn will provide a larger valid data
out window.
48. JEDEC species using tERR6-10PER when derating clock-related output timing (notes
43–44). Micron requires less derating by allowing tERR5PER to be used.
49. Requires 8 tCK for backward compatibility.
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參數(shù)描述 |
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| W3HG128M64EEU403D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU534D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU665D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU806D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
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