- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68456 > W3H128M72E2-667SBC (MICROSEMI CORP-PMG MICROELECTRONICS) 128M X 72 DDR DRAM, 1.25 ns, PBGA208 PDF資料下載
參數(shù)資料
| 型號： | W3H128M72E2-667SBC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.25 ns, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 988K |
| 代理商： | W3H128M72E2-667SBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
W3H128M72E-XSBX
25
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Clock
Clock cycle time
CL=6
tCK(6)
3,000
8,000
CL=5
tCK(5)
3,000
8,000
3,750
8,000
5,000
8,000
ps
CL=4
tCK(6)
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.48
0.52
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN (tCH, tCL)
MIN (tCH, tCL)ps
Clock
(absolute)
Absolute tCK
tCKabs
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
tCKAVG
(MIN)
+ tJITPER
(MIN)
tCKAVG
(MAX)
+ tJITPER
(MAX)
ps
Absolute CK high-level width
tCHabs
tCKAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCHAVG
(MAX)
+ tJITDTY
(MAX)
tAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCHAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
* tCHAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
* tCHAVG
(MAX)
+ tJITDTY
(MAX)
ps
Absolute CK low-level width
tCLabs
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
tCKAVG
(MIN)
*
tCLAVG
(MIN)
+ tJITDTY
(MIN)
tCKAVG
(MAX)
*
tCLAVG
(MAX)
+ tJITDTY
(MAX)
ps
Clock
Jitter
Clock jitter - period
tJITPER
-125
125
-125
125
-125
125
ps
Clock jitter - half period
tJITDUTY
-125
125
-125
125
-125
125
ps
Clock jitter - cycle to cycle
tJITCC
250
ps
Cumulative jitter error, 2 cycles
tERR2per
-175
175
-175
175
-175
175
ps
Cumulative jitter error, 3 cycles
tERR3per
-225
225
-225
225
-225
225
ps
Cumulative jitter error, 4 cycles
tERR4per
-250
250
-250
250
-250
250
ps
Cumulative jitter error, 5 cycles
tERR5per
-250
250
-250
250
-250
250
ps
Cumulative jitter error, 6-10 cycles
tERR6-10per
-350
350
-350
350
-350
350
ps
Cumulative jitter error, 11-50 cycles
tERR11-50per
-450
450
-450
450
-450
450
ps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3H128M72E2-400SBM | 128M X 72 DDR DRAM, 1.35 ns, PBGA208 |
| W3H128M72ER2-400SBM | 128M X 72 DDR DRAM, 0.6 ns, PBGA255 |
| W3H128M72ER-533SBI | 128M X 72 DDR DRAM, 0.5 ns, PBGA255 |
| W3H128M72ER-400SBI | 128M X 72 DDR DRAM, 0.6 ns, PBGA255 |
| W3H128M72ER-533SBM | 128M X 72 DDR DRAM, 0.5 ns, PBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H128M72E-400SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H128M72E-400SBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-400SBM | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-533NBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA IND TEMP. - Bulk |
| W3H128M72E-533SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。