參數(shù)資料
型號(hào): W3H128M72E0400SBM
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: DDR DRAM, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, PBGA-208
文件頁數(shù): 20/31頁
文件大?。?/td> 993K
代理商: W3H128M72E0400SBM
W3H128M72E-XSBX
27
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2008
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Command
and
Address
Address and control input pulse
width for each input
tIPW
0.6
tCK
Address and control input setup
time
tISa
400
500
600
ps
tISb
200
250
350
ps
Address and control input hold time
tIHa
400
500
600
ps
tIHb
275
375
475
ps
CAS# to CAS# command delay
tCCD
222
tCK
ACTIVE to ACTIVE (same bank)
command
tRC
55
ns
ACTIVE bank a to ACTIVE bank b
command
tRRD
10
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
Four Bank Activate period
tFAW
50
ns
ACTIVE to PRECHARGE
command
tRAS
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge
command delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery +
precharge time
tDAL
tWR + tRP
ns
Internal WRITE to READ command
delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
15
ns
PRECHARGE ALL command
period
tRPA
15
ns
LOAD MODE command cycle time
tMRD
222
tCK
Refresh
CKE low to CK, CK# uncertainty
tDELAY
tIS +tIH + tCK
ns
REFRESH to Active or Refresh to
Refresh command interval
tRFC
127.5
70,000
127.5
70,000
127.5
70,000
ns
Average periodic refresh interval
(commercial and industrial)
tREFI
7.8
μs
Average periodic refresh interval
(military)
tREFIM
1.95
μs
Exit self refresh to non-READ
command
tXSNR
tRFC(MIN) + 10
ns
Exit self refresh to READ
tXSRD
200
tCK
Exit self refresh timing reference
tlSXR
tIS
ps
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