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參數(shù)資料
| 型號： | W3H128M72E-400SBM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.35 ns, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 988K |
| 代理商： | W3H128M72E-400SBM |
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W3H128M72E-XSBX
14
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 dene the value
of AL, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AL of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
WRITE command to be issued prior to tRCD (MIN) with the
requirement that AL ≤ tRCD (MIN). A typical application using
this feature would set AL = tRCD (MIN) - 1x tCK. The READ
or WRITE command is held for the time of the AL before
it is issued internally to the DDR2 SDRAM device. RL is
controlled by the sum of AL and CL; RL = AL+CL. Write
latency (WL) is equal to RL minus one clock; WL = AL +
CL - 1 x tCK.
0
1
0
1
Mode Register Definition
M16
0
0
1
M15
High Temperature Self Refresh rate enable
Industrial temperature option;
use if T
C ex cee ds 85° C
E7
0
1
M17
0
0
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Commercial temperature default
DLL
Posted CAS#
out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
0
14
15
OCD Program
A13
A14
ODS
RTT
DQS#
RDQS
MRS
RTT
BA2
16
17
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
Note: 1. E14 (A14)-E8(A8) and E6 (A6) - E0 (A0) are reserved for future use and
must be programmed to "0." A14 is not used in this device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H128M72E-533NBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA IND TEMP. - Bulk |
| W3H128M72E-533SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H128M72E-533SBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-533SBM | 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-667SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
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