- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄68455 > W3EG7264S202BD4SG (MICROSEMI CORP-PMG MICROELECTRONICS) 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3EG7264S202BD4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | W3EG7264S202BD4SG |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
W3EG7264S-AD4
-BD4
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2005
Rev. 3
PRELIMINARY
36. Any positive glitch must be less than 1/3 of the clock cycle and not more than
+400mV or 2.9V. Any negative glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V.
37. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signicantly different voltage values.
38. VIH overshoot: VIH (MAX) = VCC + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL under-shoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
39. VCC and VCC must track each other.
40. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
41. tRPST end point and tRPRE begin point are not referenced to a specic voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
42. During initialization, VCC, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power-up, even if VCC/VCC are 0V,
provided a minimum of 42 of series resistance is used between the VTT supply
and the input pin.
43. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reect this option.
44. When an input signal is indicated to be HIGH or LOW, it is dened as a steady state
logic HIGH or LOW.
45. Random addressing changing; 50 percent of data changing at every transfer.
46. Random addressing changing; 100 percent of data changing at every transfer.
47. CKE must be active (HIGH) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satised.
48. IDD2N species the DQ, DQS and DM to be driven to a valid HIGH or LOW logic
level. IDD2Q is similar to IDD2F except IDD2Q species the address and control inputs
to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
49. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
50. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC voltage range of 2.6V±100mV.
51. The 335 speed grades will operate with tRAS(min) = 40ns and tRAS(max) = 120,000ns
at any slower frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG7264S335AD4SG | 64M X 72 DDR DRAM MODULE, 0.7 ns, DMA200 |
| W3EG7264S262AD4S | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG7264S335BD4M | 64M X 72 DDR DRAM MODULE, 0.7 ns, DMA200 |
| W3EG7264S265BD4MG | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG7264S265BD4S | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7264S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| W3EG7264S262AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL |
| W3EG7264S262BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL |
| W3EG7264S263JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| W3EG7264S265AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。