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參數(shù)資料
| 型號(hào)： | W3EG6432S265D4 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 185K |
| 代理商： | W3EG6432S265D4 |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCC = 2.5V ± 0.2V
DDR SDRAM Component Values Only
Parameter
Symbol Conditions
DDR333
@CL=2.5
Max
DDR266
@CL=2
Max
DDR266
@CL=2.5
Max
DDR266
@CL=2
Max
DDR200
@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
1000
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge;
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
1360
1280
mA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
32
mA
Idle Standby
Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
400
360
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
240
200
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
480
400
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
1400
1200
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
1400
1200
mA
Auto Refresh
Current
IDD5
tRC=tRC(MIN)
2040
1880
mA
Self Refresh
Current
IDD6
CKE 0.2V
32
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
3280
2800
mA
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|---|---|
| W3EG6432S265D4I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6432S265JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx64 DDR SDRAM UNBUFFERED |
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| W3EG6432S335D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6432S335D4I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED |
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