參數資料
型號: W3EG6432S263D4IF
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200
封裝: LEAD FREE, SO-DIMM-200
文件頁數: 10/12頁
文件大?。?/td> 185K
代理商: W3EG6432S263D4IF
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG6432S-D4
December 2004
Rev. 6
PRELIMINARY
AC OPERATING CONDITIONS
0°C TA 70°C, VCC = 2.5V ± 0.2V
AC CHARACTERISTICS
SYMBOL
335
262
263/265/202
UNITS
NOTES
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
tAC
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
7.5
13
ns
39, 44
CL = 2
tCK (2)
7.5
13
7.5
13
7.5/10
13
ns
39, 44
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.45
0.5
ns
22, 23
Write command to rst DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
30
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
tIHF
0.75
0.90
ns
12
Address and control input setup time (fast slew rate)
tISF
0.75
0.90
ns
12
Address and control input hold time (slow slew rate)
tIHS
0.80
1
ns
12
Address and control input setup time (slow slew rate)
tISS
0.80
1
ns
12
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
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