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參數(shù)資料
| 型號： | W3EG264M72EFSU335D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.7 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | W3EG264M72EFSU335D4SG |
W3EG264M72EFSUxxxD4
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2V
DDR400: VCC = VCCQ = +2.6V ±0.2V
MAX
PARAMETER/CONDITION
SYM
DDR400
@CL=3
DDR333
@CL=2.5
DDR266
@CL=2
DDR266
@CL=2.5
UNITS
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0
2475
2070
1845
mA
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC
(MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
IDD1
2745
2340
2115
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (LOW)
IDD2P
90
mA
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
IDD2F
990
810
720
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down
mode; tCK = tCK (MIN); CKE = LOW
IDD3P
810
630
540
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC =
tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
IDD3N
1080
900
810
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R
2790
2385
2115
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
IDD4W
2790
2295
2025
mA
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
IDD5
4185
3510
3330
mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD6
90
mA
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change
only during Active READ, or WRITE commands
IDD7
5130
4545
3960
mA
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