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參數(shù)資料
| 型號： | W3E64M16S-266NBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 10 X 12.50 MM, 1.50 MM HEIGHT, PLASTIC, BGA-60 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 493K |
| 代理商： | W3E64M16S-266NBM |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E64M16S-XNBX
May 2008
Rev. 0
A0-12
BA0-1
CK#
CLK
DQ0
DQ7
CKE
CS#
CS
LDM
DQM
DQ0
DQ7
WE# RAS#
A0-12
BA0-1
CLK#
CAS#
WE# RAS#CAS#
DQ8
DQ15
RAS#
WE#
CAS#
DQ0
DQ7
64Mx8
CKE
CS#
DQM
DQS
Y=
VREF
LDQS
DQS
UDM
UDQS
VREF
CLK
CK
CLK
VREF
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
After CKE passes through VIH, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable command.
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W3E64M16S-266SBC | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 266 MHZ, 60 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E64M16S-266SBI | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 266 MHZ, 60 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E64M16S-266SBM | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 266 MHZ, 60 PBGA, MIL-TEMP. - Bulk |
| W3E64M16S-333NBC | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E64M16S-333NBI | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, INDUSTRIAL TEMP. - Bulk |
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