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參數(shù)資料
| 型號(hào)： | W3100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i2Chip W3100A |
| 中文描述： | i2Chip W3100A |
| 文件頁數(shù)： | 1/63頁 |
| 文件大小： | 557K |
| 代理商： | W3100A |
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i2Chip W3100A
www.i2Chip.com
Technical Datasheet v1.1
hardware.
Description
The i2Chip W3100A is an LSI of hardware
protocol stack that provides an easy, low-cost solution
for high-speed Internet connectivity for digital devices
by allowing simple installation of TCP/IP stack in the
The W3100A offers system designers a quick,
easy way to add Ethernet networking functionality to
any product. Implementing this LSI into a system
can completely offload Internet connectivity and
processing standard protocols from the system,
thereby
significantly
reducing
development cost.
the
software
The W3100A contains TCP/IP Protocol Stacks
such as TCP, UDP, IP, ARP and ICMP protocols, as
well as Ethernet protocols such as Data Link Control
and MAC protocol.
The W3100A offers a socket API (Application
Programming Interface) that is similar to the windows
socket API. The chip offers Intel and Motorola
MCU (8051, i386, 6811 tested) bus interface and
I
2
C
for upper-layer and supports standard MII interface for
under-layer Ethernet.
The W3100A can be applied to handheld devices
including Internet phones, VoIP SOC chips, Internet
MP3 players, handheld medical devices, LAN cards
for Web servers, cellular phones and many other non-
portable electronic devices such as large consumer
electronic products.
Features
Hardware Internet protocols included:
TCP, IP Ver.4, UDP, ICMP, ARP
Hardware Ethernet protocols included:
DLC, MAC
Supports 4 independent connections simultaneously
Internal ICMP responds to PING commands
Protocol processing speed: full-duplex 4~5 Mbps
Intel/Motorola MCU bus Interface
I
2
C Interface
Standard MII Interface for under-layer physical chip
Socket API support for easy application programming
Supports full-duplex mode
Internal 16Kbytes Dual-port SRAM for data buffer
0.35 μm CMOS technology
Wide operating voltage:
3.3V internal operation, 5V tolerant 3.3V IOs
Small 64 Pin LQFP Package
Block Diagram
TCP
UDP
IP
DLC
MAC
ARP
ICMP
MII Interface
Protocol Engine
RESET
/INT
DATA(7:0)
EXT_CLK
SDA
CLOCK
MODE2
MODE1
D
M
R
R
R
T
C
T
/CS
/WR
/RD
ADDR(14:0)
/
T
/
/
SCL
MODE0
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