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| 型號： | W2Z512K72SJ35ES |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 72 MULTI DEVICE SRAM MODULE, 3.5 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 281K |
| 代理商： | W2Z512K72SJ35ES |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
W2Z512K72SJ
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDCs 72Mb
SyncBurst SRAMs integrate two 512Kx36 SRAMs into
a single BGA package to provide a 512Kx72 configura-
tion. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The NBL or No Bus Latency Memory uti-
lizes all the bandwidth in any combination of operating
cycles. Address, data inputs, and all control signals
except output enable and linear burst order are syn-
chronized to input clock. Burst order control must be
tied High or Low. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable (OE). Write
cycles are internally self-timed and initiated by the ris-
ing edge of the clock input. This feature eliminates
complex off-chip write pulse generation and provides
increased timing flexibility for incoming signals.
36Mb, 512Kx72 Synchronous Pipeline Burst NBL SRAM
FIG. 1 PIN CONFIGURATION
BLOCK DIAGRAM
(TOP VIEW)
Address Bus
(A0 - A18)
D0 - D35
D36 - D71
DQ0 - DQ71
512K x 36
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
BWA
BWB
BWC
BWD
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
BWE
BWF
BWG
BWH
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
BWA
BWB
BWC
BWD
BWA
BWB
BWC
BWD
FEATURES
n Fast clock speed: 225, 200, 166 and 150MHz
n Fast access times: 2.8, 3.0, 3.5 and 3.8ns
n Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns
n Separate Core and I/O Power Supply
n Snooze Mode for reduced-standby power
n Individual Byte Write control
n Clock-controlled and registered addresses, data
I/Os and control signals
n Burst control (interleaved or linear burst)
n Packaging:
209-bump BGA package, JEDEC Pin Definition
n Low capacitive bus loading
January 2003 Rev 1
ECO # 15888
Preliminary*
* This data sheet describes a product that may not be fully qualified
or characterized and is subject to change without notice.
12
3
4
5
6
7
8
9
10
11
A DQG
DQG
ACS2
A
ADV
A
CS2
ADQB DQB
B DQG
DQG BWC BWG
NC
WE
A
BWB BWF DQB DQB
C DQG
DQG BWH BWD
NC CS1
NC BWE BWA DQB DQB
D DQG
DQG VSS
NC
OE
NC
VSS DQB DQB
E DQPG DQPC VDDQ VDDQ VDD VDD
VDD VDDQ VDDQ DQPF DQPB
F DQC
DQC VSS
VSS
VSS NC
VSS VSS
VSS DQF DQF
G DQC
DQC VDDQ VDDQ VDD NC
VDD VDDQ VDDQ DQF DQF
H DQC
DQC VSS
VSS
VSS NC
VSS VSS
VSS DQF DQF
J DQC
DQC VDDQ VDDQ VDD NC
VDD VDDQ VDDQ DQF DQF
K
NC
CLK
NC
VSS CKE VSS NC
NC
L DQH
DQH VDDQ VDDQ VDD NC
VDD VDDQ VDDQ DQA DQA
M DQH
DQH VSS
VSS
VSS NC
VSS VSS
VSS DQA DQA
N DQH
DQH VDDQ VDDQ VDD NC
VDD VDDQ VDDQ DQA DQA
P DQH
DQH VSS
VSS
ZZ
VSS VSS
VSS DQA DQA
R DQPD DQPH VDDQ VDDQ VDD VDD
VDD VDDQ VDDQ DQPA DQPE
T DQD
DQD VSS
NC
NC LBO
NC
VSS DQE DQE
U DQD
DQD
NC
A
NC
A
NC DQE DQE
V DQD
DQD
AA
A
A1
AA
A
DQE DQE
W DQD
DQD RFU RFU
A
A0
A
RFU RFU DQE DQE
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