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  • 參數(shù)資料
    型號: W25Q32BVZEAG
    廠商: WINBOND ELECTRONICS CORP
    元件分類: PROM
    英文描述: 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
    封裝: 8 X 6 MM, GREEN, WSON-8
    文件頁數(shù): 53/79頁
    文件大小: 1090K
    代理商: W25Q32BVZEAG
    W25Q32BV
    Publication Release Date: April 01, 2011
    - 57 -
    Revision F
    7.2.36 Read SFDP Register (5Ah)
    The W25Q32BV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains
    information about device configurations, available instructions and other features. The SFDP parameters
    are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified,
    but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP
    standard initially established in 2010 for PC and other applications, as well as the JEDEC standard 1.0
    that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124
    and beyond) support the SFDP feature as specified in the applicable datasheet.
    The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah”
    followed by a 24-bit address (A23-A0)
    (1) into the DI pin. Eight “dummy” clocks are also required before the
    SFDP register contents are shifted out on the falling edge of the 40
    th CLK with most significant bit (MSB)
    first as shown in Figure 34. For SFDP register values and descriptions, refer to the following SFDP
    Definition table.
    Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.
    /CS
    CLK
    DI
    (IO
    0)
    DO
    (IO
    1)
    Mode 0
    Mode 3
    0
    1
    2
    3
    4
    5
    6
    7
    Instruction (5Ah)
    High Impedance
    8
    9
    10
    28
    29
    30
    31
    24-Bit Address
    23
    22
    21
    3
    2
    1
    0
    Data Out 1
    *
    /CS
    CLK
    DI
    (IO
    0)
    32
    DO
    (IO
    1)
    33
    34
    35
    36
    37
    38
    39
    Dummy Byte
    High Impedance
    40
    41
    42
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    7
    6
    5
    4
    3
    2
    1
    0
    7
    Data Out 2
    7
    6
    5
    4
    3
    2
    1
    0
    43
    31
    0
    *
    7
    6
    5
    4
    3
    2
    1
    0
    *
    = MSB
    *
    Figure 34. Read SFDP Register Instruction Sequence Diagram
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