- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68427 > W25Q16CLSFIP (WINBOND ELECTRONICS CORP) 16M X 1 SPI BUS SERIAL EEPROM, PDSO16 PDF資料下載
參數(shù)資料
| 型號(hào)： | W25Q16CLSFIP |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 16M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| 封裝： | 0.300 INCH, GREEN, PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 39/77頁(yè) |
| 文件大?。?/td> | 2458K |
| 代理商： | W25Q16CLSFIP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)
W25Q16CL
- 44 -
11.2.25 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2). The Block
Erase instruction sequence is shown in figure 23.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle
is in progress, the Read Status Register instruction may still be accessed for checking the status of the
BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Status Register Memory Protection table).
Figure 23. 64KB Block Erase Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25Q16CLDAIG | 16M X 1 SPI BUS SERIAL EEPROM, PDIP8 |
| W25Q16CLZPIP | 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q16CLSFIG | 16M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q16CVSSIG | 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q16DWZPIP | 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q16CLSNIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CLSNIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CLSSIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CLSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CLZPIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。