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參數(shù)資料
| 型號(hào)： | W25P025A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K×32 Burst Pipeline High-Speed CMOS Static RAM(64K×32位同步脈沖管線高速CMOS靜態(tài)RAM) |
| 中文描述： | 64K的管道爆裂× 32高速CMOS靜態(tài)RAM（64K的× 32位同步脈沖管線高速的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | W25P025A |
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W25P025A
64K
×
32 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
Publication Release Date: January 1998
- 1 -
Revision A3
GENERAL DESCRIPTION
The W25P025A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM
organized as 65,536
×
32 bits that operates on a dual 3.3/2.5-volt power supply. It is designed for
mobile Pentium system. A built-in two-bit burst address counter supports both Pentium
burst mode
and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-
pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation.
The W25P025A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The
default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to V
DDQ
. The state of
pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data
output in a burst read cycle when the device is deselected by CE2/
CE3
. This mode supports 3-1-1-1-
1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables
data output within one cycle in a burst read cycle when the device is deselected by CE2/
CE3
. In this
mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation
High-speed access time: 6/7 nS (max.)
Dual 3.3/2.5V power supply
Individual byte write capability
Clock-controlled and registered input
Asynchronous output enable
Pipelined/non-pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst mode
& linear burst mode
Supports both 2T/2T & 2T/1T mode
Packaged in 100-pin QFP or TQFP
BLOCK DIAGRAM
A(15:0)
DATA I/O
REGISTER
INPUT
REGISTER
CONTROL
LOGIC
REGISTER
64K X 32
CORE
ARRAY
CE(3:1)
BWE
CLK
OE
GW
ADSC
ADSP
ADV
LBO
BW(4:1)
I/O(32:1)
FT
ZZ
MS
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