參數(shù)資料
型號(hào)： W256HT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： 12 Output Buffer for 2 DDR and 3 SRAM DIMMS
中文描述： 256 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝： 5.30 MM, SSOP-28
文件頁(yè)數(shù)： 1/9頁(yè)
文件大?。?/td> 176K
代理商： W256HT
12 Output Buffer for 2 DDR and 3 SRAM DIMMS
W256
Cypress Semiconductor Corporation
Document #: 38-07256 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 30, 2004
Features
One input to 12 output buffer/drivers
Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS
One additional output for feedback
SMBus interface for individual output control
Low skew outputs (< 100 ps)
Supports 266 MHz and 333 MHz DDR SDRAM
Dedicated pin for power management support
Space-saving 28-pin SSOP package
Functional Description
The W256 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 12 outputs.
Designers can configure these outputs to support 3 unbuffered
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can
be used in conjunction with the W250-02 or similar clock
synthesizer for the VIA Pro 266 chipset.
The W256 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull-up).
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Block Diagram
SMBus
Decoding
&
Powerdown
Control
BUF_IN
SDATA
SCLOCK
DDR0T_SDRAM0
DDR0C_SDRAM1
DDR1T_SDRAM2
DDR1C_SDRAM3
SSOP
Top View
Pin Configuration
[1]
DDR2T_SDRAM4
DDR2C_SDRAM5
DDR3T_SDRAM6
DDR3C_SDRAM7
DDR4T_SDRAM8
PWR_DWN#
DDR4C_SDRAM9
DDR5T_SDRAM10
DDR5C_SDRAM11
FBOUT
SEL_DDR
FBOUT
*PWR_DWN#
DDR0T_SDRAM0
DDR0C_SDRAM1
VDD3.3_2.5
GND
DDR1T_SDRAM2
DDR1C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR2T_SDRAM4
DDR2C_SDRAM5
VDD3.3_2.5
SEL_DDR*
DDR5T_SDRAM10
DDR5C_SDRAM11
VDD3.3_2.5
GND
DDR4T_SDRAM8
DDR4C_SDRAM9
VDD3.3_2.5
GND
DDR3T_SDRAM6
DDR3C_SDRAM7
GND
SCLK
SDATA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDD3.5_2.5
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