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參數(shù)資料
| 型號： | W24LH8Q-70SL |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, TSOP1-28 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 186K |
| 代理商： | W24LH8Q-70SL |
Preliminary W24LH8
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS
WE
D OUT
DIN
TWC
T WR
TCW
T WP
TAS
TOHZ
(1, 4)
TDW
TDH
TAW
Write Cycle 2
(OE = VIL Fixed)
Address
CS
WE
DOUT
DIN
T WC
TCW
TAS
TDH
TWR
TWP
TWHZ
DW
T
(2)
(3)
TOW
TOH
AW
T
(1, 4)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured
±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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