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參數(shù)資料
| 型號： | W24L010AT-15 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 High Speed CMOS Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 8 X 20 MM, TSOP1-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 152K |
| 代理商： | W24L010AT-15 |
W24L010A
- 6 -
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
Address
OE
CS1
CS2
WE
D
D
T
T
(1, 4)
OUT
IN
OHZ
WC
T
WR1
T
CW1
T
CW2
T
AW
T
WP
T
WR2
T
AS
T
DW
T
DH
Write Cycle 2
(
OE
= V
IL
Fixed)
Address
CS1
CS2
WE
D
D
T
T
T
T
T
T
T
T
T
T
T
(2)
(3)
T
T
WC
CW1
WR1
CW2
AW
WP
WR2
OW
WHZ (1, 4)
DW
DH
OH
AS
OUT
IN
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from D
OUT
are the same as the data written to D
IN
during the write cycle.
3. Dout provides the read data for the next address.
4. Transition is measured
±
500 mV from steady state with C
L
= 5 pF. This parameter is guaranteed but not 100% tested.
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